MCST-R500S
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| General information | |
|---|---|
| Launched | 2007 |
| Designed by | Moscow Center of SPARC Technologies (MCST) |
| Common manufacturer | Page Template:Plainlist/styles.css has no content. |
| Performance | |
| Max. CPU clock rate | 500 MHz |
| Physical specifications | |
| Cores | Page Template:Plainlist/styles.css has no content.
|
| Architecture and classification | |
| Instruction set | SPARC V8 |
The MCST R500S (Template:Langx) is a 32-bit system-on-a-chip, developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.
MCST R500S Highlights
- implements the SPARC V8 instruction set architecture (ISA)
- dual-core
- the two cores can work in redundancy to increase reliability of the system.
- core specifications:
- shared 512KB L2 cache
- integrated controllers:
- 500 МHz clock rate
- 130 nm process
- die size 100 mm2
- ~45 million transistors
- power consumption 5W
References
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