Wide-issue
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A wide-issue architecture is a computer processor that issues more than one instruction per clock cycle.[1] They can be considered in three broad types:
- Statically-scheduled superscalar architectures execute instructions in the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.
- VLIW architectures rely on the programming software (compiler) to determine which instructions to dispatch on a given clock cycle.[2]
- Dynamically-scheduled superscalar architectures execute instructions in an order that gives the same result as the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.[3]
See also
References
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- ^ Page Module:Citation/CS1/styles.css has no content."Scheduling for Superscalar & Multiple Issue Machines" (PDF).
- ^ Page Module:Citation/CS1/styles.css has no content."Wide Issue and Speculation". Archived from the original on 2016-03-04. Retrieved 2015-10-23.
- ^ Page Module:Citation/CS1/styles.css has no content.Martin, Milo. "Superscalar" (PDF). Archived from the original (PDF) on 2021-10-09. Retrieved 2015-10-30.
